3D hardware canaries

Sébastien Briais, Stéphane Caron, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, Jacques-Henri Jourdan, Arthur Milchior, David Naccache, and Thibault Porteboeuf. Cryptographic Hardware and Embedded Systems, Springer, 2012.

Abstract

3D integration is a promising advanced manufacturing process offering a variety of new hardware security protection opportunities. This paper presents a way of securing 3D ICs using Hamiltonian paths as hardware integrity verification sensors. As 3D integration consists in the stacking of many metal layers, one can consider surrounding a security-sensitive circuit part by a wire cage. After exploring and comparing different cage construction strategies (and reporting preliminary implementation results on silicon), we introduce a "hardware canary". The canary is a spatially distributed chain of functions Fi positioned at the vertices of a 3D cage surrounding a protected circuit. A correct answer (Fn ∘ … ∘ F1)(m) to a challenge m attests the canary's integrity.

BibTeX

@inproceedings{briais2012ches,
  title = {3D Hardware Canaries},
  author = {Briais, S{\'e}bastien and Caron, St{\'e}phane and Cioranesco, Jean-Michel and Danger, Jean-Luc and Guilley, Sylvain and Jourdan, Jacques-Henri and Milchior, Arthur and Naccache, David and Porteboeuf, Thibault},
  booktitle = {Cryptographic Hardware and Embedded Systems},
  pages = {1--22},
  year = {2012},
  publisher = {Springer},
  doi = {10.1007/978-3-642-33027-8_1}
}
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