I recently wrote down a short introduction to GNU make (in French). If you already understand the rules of the following Makefile, it’s actually not worth reading it ;-) But here is the practical use case:
SRC = *.c OBJ = $(SRC:.c=.o) BIN = mybin CFLAGS = -Wall -O2 all: $(BIN) $(BIN): $(OBJ) gcc $^ $(CFLAGS) -o $@ %.o: %.c gcc -c $^ $(CFLAGS) -o $@
This simple Makefile will look for all C files in its directory, compile them
to intermediate object files, then gather all these object files into one
binary called mybin. Assuming you put the Makefile and C files together
in the same folder, all you have to do is run:
$ make
This will call the default all rule, which depends on the binary,
triggering the $(BIN) rule, which depends on all object files. Since
there is a generic rule to compile %.o files from %.c files,
Make will automatically infer what it should do, compile the source files into
objects, then bind them all into the binary. Mission accomplished.
I hope this template can be as handy for you as it is for me. I always forget
the special variables ($^ and $@) required to write down the generic
rule, so I keep the template here and come back to copy-paste it once in a
while ;-)
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